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12-bit ccd signal processor with precision timing core ad9949 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features new a d 994 9a supports ccd li ne length > 40 96 pixels correlated dou b le sampler (c ds) 0 db to 18 db pixel gain ampli f ier (pxg a?) 6 db to 42 db 1 0 -bit vari able g a in amplifier (vga) 12-bit, 36 msp s analog-to-di gital converter (adc) black leve l cla m p with variab le le vel control complete on-chip timing driver precision timing? core with < 600 ps resol u ti on on-chip 3 v horizontal and r g dri v ers 40-lea d lfcsp package applic ati o ns digital sti ll ca meras high speed digital imaging ap plications general description the ad9949 is a hig h l y in t e g r a t ed c c d sig n a l p r o c es s o r f o r dig i t a l st i l l camera a p pli c a t io n s . s p e c if ie d a t p i xe l ra t e s o f u p to 36 mh z, t h e ad9949 co n s is ts o f a co m p let e analog f r o n t en d wi th a/d con v ersio n , co m b in e d wi t h a p r og ra mma b l e t i min g dr i v er . th e pr e c is io n t i m i n g co r e allo w s ad j u s t m e n t o f h i g h s p eed c l o c ks wi t h < 600 ps r e s o l u tio n . the a n a l og f r o n t end i n cl u d es black l e vel clam pin g , cds, pxga, v g a, and a 36 ms ps, 12 -b i t ad c. th e t i min g dr i v er p r o v ide s t h e hi g h sp e e d c c d cl o c k dr i v ers fo r rg a nd h1 to h4. o p era t ion is p r og ra mm e d usin g a 3-wir e s e r i al in ter f ace . p a c k a g ed i n a s p a c e - sa vi n g , 40- l ea d l f cs p pac k a g e , th e ad9949 is s p ec if ied o v er a n o p era t in g tem p era t ur e ra n g e o f ?20c t o +85c. func tio n a l block di agram clamp dout ccdin reft refb internal registers 6db to 42db sync generator sdata sck sl hblk vga ad9949 precision timing core 12-bit adc v ref internal clocks pxga cds horizontal drivers rg h1 to h4 hd vd cli clp/pblk 0db to 18db 03751-001 4 12 fi g u r e 1 .
ad9949 rev. b | page 2 of 36 table of contents specifications..................................................................................... 3 general specifications ................................................................. 3 digital specifications ................................................................... 3 analog specifications................................................................... 4 timing specifications .................................................................. 5 absolute maximum ratings............................................................ 6 thermal characteristics .............................................................. 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 terminology ...................................................................................... 8 equivalent input/output circuits .................................................. 9 typical performance characteristics ........................................... 10 system overview ............................................................................ 11 h-counter behavior .................................................................. 11 serial interface timing .................................................................. 12 complete register listing ............................................................. 13 precision timing high speed timing generation...................... 18 timing resolution...................................................................... 18 high speed clock programmability ........................................ 18 h-driver and rg outputs ........................................................ 19 digital data outputs.................................................................. 19 horizontal clamping and blanking ............................................. 21 individual clpob and pblk sequences................................ 21 individual hblk sequences..................................................... 21 generating special hblk patterns .............................................. 23 horizontal sequence control ................................................... 23 external hblk signal................................................................ 23 h-counter synchronization ..................................................... 24 power-up procedure...................................................................... 25 recommended power-up sequence ....................................... 25 analog front end description and operation .......................... 26 dc restore .................................................................................. 26 correlated double sampler ...................................................... 26 pxga............................................................................................ 26 variable gain amplifier ............................................................ 29 adc ............................................................................................. 29 optical black clamp .................................................................. 29 digital data outputs.................................................................. 29 applications information .............................................................. 30 circuit configuration ................................................................ 30 grounding and decoupling recommendations.................... 30 driving the cli input................................................................ 31 horizontal timing sequence example.................................... 31 outline dimensions ....................................................................... 34 ordering guide .......................................................................... 34 revision history 11 /04data sheet changed from rev. a to rev. b changes to ordering guide .......................................................... 35 9/04data sheet changed from rev. 0 to rev. a changes to features.......................................................................... 1 changes to analog specifications .................................................. 4 changes to terminology section.................................................... 9 added h-counter behavior section............................................ 12 changes to table 7.......................................................................... 14 changes to table 12 ....................................................................... 17 changes to table 15 ....................................................................... 17 changes to h-counter sync section ........................................... 24 changes to recommended power-up sequence section ......... 25 changes to ordering guide .......................................................... 35 5/03revision 0: initial version
ad9949 rev. b | page 3 of 36 specifications general specifications table 1. parameter min typ max unit temperature range operating ?20 +85 c storage ?65 +150 c maximum clock rate 36 mhz power supply voltage avdd, tcvdd (afe, timing core) 2.7 3.0 3.6 v hvdd (h1 to h4 drivers) 2.7 3.0 3.6 v rgvdd (rg driver) 2.7 3.0 3.6 v drvdd (d0 to d11 drivers) 2.7 3.0 3.6 v dvdd (all other digital) 2.7 3.0 3.6 v power dissipation 36 mhz, hvdd = rgvdd = 3 v, 100 pf h1 to h4 loading 1 320 mw total shutdown mode 1 mw 1 the total power dissipated by the hvdd suppl y may be approximated using the equation total hvdd power = (cload x hvdd x pixel frequency) x hvdd x (number of h C outputs used) reducing the h-loading, using only two of the outputs, and/or using a lower hvdd supply, reduces the power dissipation. digital specifications t min to t max , avdd = dvdd = drvdd = hvdd = rgvdd = 2.7 v, c l = 20 pf, unless otherwise noted. table 2. parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v cli input high level input voltage (tcvdd/2 + 0.5 v) v ihCcli 1.85 v low level input voltage v ilCcli 0.85 v rg and h-driver outputs high level output voltage (rgvdd C 0.5 v and hvdd C 0.5 v) v oh 2.2 v low level output voltage v ol 0.5 v maximum output current (programmable) 30 ma maximum load capacitance 100 pf
ad9949 r e v. b | pa ge 4 o f 3 6 analog s p ecifica t ions t min to t max , a v d d = d v dd = 3.0 v , f cli = 3 6 m h z , t y pi c a l t i m i ng s p e c i f i c a t i o ns , u n l e ss ot he r w i s e note d. table 3. parameter min typ max unit notes c d s g a i n 0 d b allow a ble ccd reset t r ansient 1 5 0 0 m v maximum input range before saturation 1 1.0 v p-p maximum ccd blac k pixel amplitude 1 50 mv pixel g a in am plifier (pga) gain control re solution 256 steps gain monotonicity minimum gain 0 db maximum gain 18 db variable gain amplifie r ( v ga ) maximum input range 1.0 v p-p max imum output range 2.0 v p-p gain control re solution 1024 steps gain monotonicity guaranteed gain range minimum gain (vga code 0) 6 db max imum gain (vga code 10 23 ) 42 db black level c l amp clamp leve l resolution 256 steps clamp level measured at ad c output minimum clamp level (0) 0 lsb maximum clam p level (255) 255 lsb a/d convert e r r e s o l u t i o n 1 2 b i t s differential non l inearity (dnl) ?1.0 0.5 +1.0 lsb no m i ssing cod e s guaranteed integral nonlinearity (in l ) 8 lsb full-scale input voltage 2.0 v voltage refer e nce reference top voltage (reft) 2.0 v reference bottom voltage (refb ) 1.0 v system p e rformance specificat ion s in clude entire signal cha i n vga gain accur a cy minimum gain (code 0) 5.0 5.5 6.0 db maximum gain (code 1023) 40.5 41.5 42.5 db peak nonlineari ty, 500 mv input signal 0.15 0.6 % 12 db gain appli e d total output no ise 0.8 lsb rms ac grounded in put, 6 db gain a pplied power supply rejection (psr) 50 db measured with step change on supply 1 in put si gn a l ch a r a c t e ri st i c s d e fi n e d a s fol l ow s: 50mv max optical black pixel 500mv typ reset transient 1v max input signal range 03751-002
ad9949 rev. b | page 5 of 36 timing specifications c l = 20 pf, f cli = 36 mhz, unless otherwise noted. table 4. parameter symbol min typ max unit master clock (cli) (see figure 16) cli clock period t cli 27.8 ns cli high/low pulse width t adc 11.2 13.9 16.6 ns delay from cli to internal pixel period position t clidly 6 ns clpob pulse width (programmable) 1 t cob 2 20 pixels sample clocks (see figure 18) shp rising edge to shd rising edge t s1 12.5 13.9 ns data outputs (see figure 19 and figure 20) output delay from programmed edge t od 6 ns pipeline delay 11 cycles serial interface (serial timing shown in figure 14 and figure 15) maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns sck falling edge to sdata valid read t dv 10 ns 1 minimum clpob pulse width is for functional operation only. wi der typical pulses are recommended to achieve low noise clamp re ference.
ad9949 r e v. b | pa ge 6 o f 3 6 absolute maximum ratings table 5. parameter with respect to rating avdd and tc v dd avss ?0.3 v to +3.9 v hvdd and rg v dd hvss, rgvss ?0.3 v to +3.9 v dvdd and dr v dd dvss, drvss ?0.3 v to +3.9 v any vss any vss ?0.3 v to +0.3 v digital outputs drvss ? 0 . 3 v t o d r v d d + 0 . 3 v clpob/pblk and hblk dvss ?0.3 v to dvdd + 0.3 v sck, sl, and sd ata dvss ?0.3 v to dvdd + 0.3 v rg rgvss ? 0 . 3 v t o r g v d d + 0 . 3 v h1 to h4 hvss ?0.3 v to hvdd + 0.3 v reft, refb, and ccdin avss ?0.3 v to avdd + 0.3 v junction tempe r ature 150c l e a d t e m p e r a t u r e ( 1 0 s ) 300c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e maxi- m u m r a t i ng co ndi t i on s fo r ex ten d e d p e r i o d s m a y a f fe c t de v i ce rel i abi l it y . thermal c h aracteristics ther ma l resi st anc e 40-l e ad lfcs p p a c k a g e: ja = 27c/w 1 . 1 ja i s m e a s ure d usi n g a 4- la yer pc b wi t h t h e expos e d pa d dle s o l d er ed t o t h e board. esd caution esd (electrostatic discharge) sensitive device. ele c tr ostatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharg e wit h out detection. althou gh this product features proprietary esd protection circu i try, permanent damage may occur on devices s u bjec ted to high energy elec- trostatic dischar g es. t h erefore, proper esd prec aution s are reco mmended to avoid performanc e degradation or los s of functionality.
ad9949 r e v. b | pa ge 7 o f 3 6 pin conf iguration and fu nction descriptions 03751-003 ad9949 top view 1 d1 d8 d7 d6 d5 drvdd drvss d4 d3 d2 2 3 4 5 6 7 8 9 10 r g vss h4 h3 hv dd h vss h2 h1 (ms b ) d1 1 d1 0 d9 11 12 13 14 15 16 17 18 19 20 30 refb rg rgvdd tcvss tcvdd cli avdd ccdin avss reft 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 sl d0 (ls b ) c l p/pb lk hblk dv dd d vss hd vd sc k sd i pin 1 indicator f i gure 2. pin config ur ation ta ble 6. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic type 1 description 1 to 4 d1 to d4 do data outputs 5 drvss p digital driver ground 6 drvdd p digital driver supply 7 to 13 d5 to d11 do da ta outputs (d 11 is msb) 14 h1 do ccd horizontal clock 1 15 h2 do ccd horizontal clock 2 16 hvss p h1 to h4 driver ground 17 hvdd p h1 to h4 driver supply 18 h3 do ccd horizontal clock 3 19 h4 do ccd horizontal clock 4 20 rgvss p rg driver ground 21 rg do ccd reset gate clock 22 rgvdd p rg driver supply 23 tcvss p analog ground for timing core 24 tcvdd p analog supply f o r timing core 25 cli di master clock in put 26 avdd p analog supply f o r afe 27 ccdin ai analog input for ccd signal (connect through series 0.1 f capacitor) 28 avss p analog ground for afe 29 reft ao reference top decoupli ng (de c ouple with 1.0 f to avss) 30 refb ao reference bottom decoupli ng (decouple with 1 . 0 f to avss ) 31 sl di 3-wire serial load 32 sdi di 3-wire serial data input 33 sck di 3-wire serial clock 34 vd di vertical sync pulse 35 hd di horizontal sync pulse 36 dvss p digital ground 37 dvdd p digital supply 38 hblk di optional hblk input 39 clp/pblk do c lpob or pblk output 40 d0 do data output ls b 1 type: ai = an a l og i n put , ao = an a l og out p ut , d i = d i g i t a l in put , d o = d i g i t a l out p ut , p = pow e r.
ad9949 rev. b | page 8 of 36 terminology differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus, every code must have a finite width. no missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. integral nonlinearity (inl) inl is the deviation of each individual code measured from a true straight line from zero to full scale. the point used as zero scale occurs 0.5 lsb before the first code transition. positive full scale is defined as a level 1 lsb and 0.5 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. peak nonlinearity peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the ad9949 from a straight line. the point used as zero scale occurs 0.5 lsb before the first code transition. positive full scale is defined as a level 1 lsb and 0.5 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the straight line reference. the error is then expressed as a percentage of the 2 v adc full-scale signal. the input signal is appropriately gained up to fill the adcs full-scale range. tot a l o utput noi s e the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and represents the rms noise level of the total signal chain at the specified gain setting. the output noise can be con- verted to an equivalent voltage, using the relationship 1 lsb = ( adc full scale / 2 n codes ) where n is the bit resolution of the adc. for the ad9949, 1 lsb is approximately 0.488 mv. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. the psr specification is calculated from the change in the data outputs for a given step change in the supply voltage.
ad9949 r e v. b | pa ge 9 o f 3 6 equivalent input/output circuits r avdd avss avss 03751-004 f i gure 3. c c din (pin 27) avdd avss 330 ? cli 25k ? 1.4v 03751-005 + f i g u re 4. cli (pin 25 ) dvss drvdd dvss drvss data three-state dout 03751-006 f i gur e 5 . da t a out p uts d0 to d1 1 (p i n s 1 to 4, 7 to 13 , 40 ) 03751-007 dvdd dvss 330 ? f i g u re 6. d i g i t a l in put s (p ins 3 1 t o 35, 38) 03751-008 hvdd or rgvdd hvss or rgvss data enable dout f i g u re 7. h1 to h 4 and r g (p ins 1 4 t o 15, 1 8 t o 19, 2 1 )
ad9949 rev. b | page 10 of 36 typical perf orm ance cha r acte ristics 03751-009 adc output code 4000 0 500 1000 1500 2000 2500 3000 3500 dnl (ls b ) 1.0 0.5 0 ? 0.5 ? 1.0 fi g u r e 8 . t y p i c a l d n l 03751-010 vga gain code (lsb) 1000 0 200 400 600 800 ou tpu t n o ise ( l sb ) 48 40 32 24 16 8 0 f i g u re 9. o u t p ut n o is e v s . v g a g a in 03751-011 sample rate (mhz) 36 18 24 30 pow e r d i ssipa tion ( m w ) 400 350 300 250 200 150 v dd = 3.3v v dd = 3.0v v dd = 2.7v f i g u re 10. p o wer cur v es
ad9949 rev. b | page 11 of 36 system overview ccd serial interface dout digital image processing asic v-driver hd, vd cli v1 to vx, vsg1 to vsgx, subck h1 to h4, rg ccdin ad9949 integrated afe + td 03751- 012 f i gure 11. t y pic a l a p plic at ion f i gur e 11 sh o w s t h e typ i cal sys t em a p pl ic a t io n dia g ram fo r t h e ad9949. the c c d o u t p u t is p r o c es s e d b y t h e ad9949 s afe cir c ui t r y , w h ich co n s ists o f a c d s, a pxga, a v g a, a b l ack l e vel cla m p , an d an ad c. t h e d i g i t i ze d p i xel info r m a t io n is s e n t to t h e dig i t a l ima g e p r o c es s o r chi p w h er e al l p o st pr o c es sin g an d co m p r e s s io n o c c u rs. t o o p era t e t h e c c d , c c d t i mi n g p a ra m e t e rs a r e p r og ra mm ed in t o th e ad9949 f r o m the ima g e pro c e s s o r t h rou g h t h e 3 - w i re s e r i a l i n te r f a c e. f r om t h e s y ste m mas t er clo c k, c l i, p r o v i d e d b y t h e ima g e p r o c e s s o r , t h e ad9949 g e n e ra t e s t h e hig h sp e e d ccd c l o c ks a nd al l in t e r n al afe c l o c ks. al l ad9949 c l o c ks a r e syn c hr o n ize d wi t h vd and hd . th e a d 99 49 s h o r i zo n t al p u ls es (clpo b , p b lk, an d hb lk) a r e p r ogra mm e d an d g e n e ra t e d in t e r n al l y . the h- dr i v ers fo r h1 t o h4 a nd r g a r e i n cl u d e d i n t h e ad9949, al lo win g t h es e c l o c ks t o be dir e c t l y conn ec t e d t o t h e ccd . th e h-dr i v e v o l t a g e o f 3 v is s u p p o r t e d in t h e ad9949. fi g u r e 1 2 s h ow s t h e h o r i z o nt a l a n d v e r t i c a l c o u n t e r d i m e n s i o n s f o r th e ad9949. al l in t e r n al h o r i zon t al c l o c k i n g is p r og ra mm ed u s i n g t h e s e d i m e ns i o ns to sp e c i f y l i ne a n d pi x e l l o c a t i on s . h-counter behavior w h en t h e maxim u m h o r i zo n t a l co un t o f 4096 p i xe ls is exceeded , t h e h - co un t e r in the ad9949 r o l l s o v er t o zer o a nd c o n t i n u e s c o u n ti n g . i t i s , th e r e f o r e , r e c o m m e n d e d t h a t th e m a xi m u m co un t e r v a l u e n o t be e x ceed ed . h o w e v e r , t h e n e w e r ad9949a versio n b e ha v e s dif f er en tl y . i n th e ad9949 a, t h e in t e r n al h-c o un t e r h o lds a t i t s max i m u m co un t o f 4095 in s t ead o f r o l l ing o v er . this f e a t ur e al lo ws t h e ad9949a t o be us ed in a p p l ica t io n s co n t aining a lin e len g th gr ea t e r tha n 4096 p i x e ls. al th o u gh n o p r ogra mma b l e val u es f o r t h e hor i z o n t a l b l an k i ng or cl a m pi ng are a v ai l a b l e b e y o nd pi xel 4095, th e h, r g , a nd afe c l o c k i n g co n t in ues t o o p era t e , s a m p ling t h e r e ma inin g p i xe ls o n t h e line . maximum field dimensions 12-bit horizontal = 4096 pixels max 12-bit vertical = 4096 lines max 03751-013 f i g u re 12. v e r t ic al and ho ri z o nt al co unters vd hd cli max hd length is 4095 pixels 03751-014 max vd length is 4095 lines f i g u re 13. m a x i mu m v d /hd d i me ns i o ns
ad9949 rev. b | page 12 of 36 serial interface timing the ad9949 s in t e r n al r e g i st ers a r e acces s e d thr o ug h a 3-wir e s e r i a l in ter f ace. e a ch r e g i ster con s ists o f a n 8- b i t addr ess a nd a 24-b i t da t a -w o r d . b o t h t h e 8- b i t addr ess a nd 24 -b i t da t a - w o r d a r e w r i t t e n s t a r ti n g w i th th e l s b . t o w r i t e t o e a c h r e gi s t e r , a 32-b i t o p era t ion is r e q u ir e d , as sho w n i n f i gur e 14. alt h oug h ma n y r e g i s t ers a r e les s tha n 24 b i ts wide , al l 24 b i ts m u s t be wr i t t e n fo r e a ch r e g i s t er . i f t h e reg i s t er is o n l y 1 6 b i ts w i de , t h e n t h e u p p e r e i g h t b i ts ma y b e f i l l e d w i t h zer o s d u r i n g t h e s e r i a l wr i t e o p era t io n. i f fe w e r t h a n 2 4 b i ts a r e wr i t t e n, t h e r e g i st er wi l l n o t b e up da te d wi t h ne w d a t a . f i gur e 15 sh o w s a m o r e ef f i cien t wa y t o wr i t e t o t h e r e g i s t ers b y usin g the ad99 49 s addr es s a u to-in c r e m e n t ca p a b i li ty . u s in g t h is met h o d , t h e lo w e st des i r e d addr ess is wr i t ten f i rst, fol l o w e d b y m u l t i p le 24-b i t da t a -w o r ds. e a c h n e w 24-b i t da ta-w o r d is w r it te n a u toma t i c a l l y to t h e ne x t h i g h e s t re g i ste r a ddre s s . by e l imina t in g t h e n e e d t o wr i t e e a ch 8-b i t addr es s , fas t er r e g i s t er lo adin g is ach i e v e d . a ddr ess a u t o -i n c r e m e n t m a y b e us e d st a r t - in g wi t h an y r e g i s t er lo ca tio n and ma y be us e d to wr i t e t o as f e w as tw o r e g i s t ers o r as ma n y as t h e en t i r e r e g i s t er s p ace . sdat a a0 a1 a2 a4 a5 a6 a7 d0 d1 d2 d3 d21 d22 d23 sck sl a3 notes 1. individual sdata bits are latched on sck rising edges. 2. all 32 bits must be written: 8 bits for address and 24 bits for data. 3. if the register length is <24 bits, then don?t care bits must be used to complete the 24-bit data length. 4. new data is updated at either the sl rising edge or at the hd falling edge after the next vd falling edge. 5. vd/hd update position may be delayed to any hd falling edge in the field using the update register. vd sl updated vd/hd updated hd ... ... ... ... ... 8-bit address 24-bit data 1 32 2 3 4 5 6 7 8 9 10 11 12 30 31 03751-015 t ls t ds t dh t lh f i gure 14. s e ri al wr ite o p er ati o n sdata a0 a1 a2 a4 a5 a6 a7 d0 d1 d22 d23 sck sl a3 notes 1. multiple sequential registers may be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 24-bit data-words. 3. the address will automatically increment with each 24-bit data-word (all 24 bits must be written). 4. sl is held low until the last desired register has been loaded. 5. new data is updated at either the sl rising edge or at the hd falling edge after the next vd falling edge. d0 d1 d22 d23 d0 ... ... ... data for starting register address data for next register address d2 d1 ... ... ... ... ... ... 1 32 23 45 6 7 89 1 0 3 1 34 33 56 55 58 57 59 03751-016 f i gure 15. cont in u o us s e ri a l write o p er at ion
ad9949 rev. b | page 13 of 36 complete register listing 1. all addresses and default values are expressed in hexadecimal. 2. all registers are vd/hd updated as shown in figure 14, except for the registers indicated in table 7, which are sl updated. table 7. sl updated registers register description oprmode afe operation modes ctlmode afe control modes sw_reset software reset bit tgcore _rstb reset bar signal for internal tg core preventupdate prevents update of registers vdhdedge vd/hd active edge fieldval resets internal field pulse hblkretime retimes the hblk to internal clock clpblkout clp/blk output pin select clpblken enables clp/blk output pin h1control h1/h2 polarity/edge control rgcontrol rg polarity/edge control drvcontrol rg and h1 to h4 drive current sampcontrol shp/shd sa mpling edge control doutphase data output phase adjustment
ad9949 rev. b | page 14 of 36 table 8. afe register map address data bit content default value name description 00 [11:0] 4 oprmode afe operation modes. (see table 14.) 01 [9:0] 0 vgagain vga gain. 02 [7:0] 80 clamp level optical black clamp level. 03 [11:0] 4 ctlmode afe control modes. (see table 15.) 04 [17:0] 0 pxga gain01 pxga gain regi sters for color 0 [8:0] and color 1 [17:9]. 05 [17:0] 0 pxga gain23 pxga gain regi sters for color 2 [8:0] and color 3 [17:9]. table 9. miscellaneous register map address data bit content default value name description 10 [0] 0 sw_rst software reset. 1 = reset all registers to default, then self-clear back to 0. 11 [0] 0 out_control output control. 0 = make all dc outputs inactive. 12 [0] 0 tgcore_rstb timing core reset bar. 0 = reset tg core. 1 = resume operation. 13 [11:0] 0 update serial update. sets the line (hd) within the field to update serial data. 14 [0] 0 preventupdate prevents the update of the vd updated registers. 1 = prevent update. 15 [0] 0 vdhdedge vd/hd active edge. 0 = falling edge triggered. 1 = rising edge triggered. 16 [1:0] 0 fieldval field value sync. 0 = next field 0. 1 = next field 1. 2/3 = next field 2. 17 [0] 0 hblkretime retime hblk to internal h1 clock. preferred setting is 1. setting to 1 adds one cycle delay to hblk toggle positions. 18 [1:0] 0 clpblkout clp/blk pin output select. 0 = clpob. 1 = pblk. 2 = hblk. 3 = low. 19 [0] 1 clpblken enable clp/blk output. 1 = enable. 1a [0] 0 test mode internal test mode. should always be set high.
ad9949 rev. b | page 15 of 36 table 10. clpob register map address data bit content default value (hex) name description 20 [3:0] f clpobpol start polarities for clpob sequences 0, 1, 2, and 3. 21 [23:0] ffffff clpobtog_0 sequence 0. toggle position 1 [11:0] and toggle position 2 [23:12]. 22 [23:0] ffffff clpobtog_1 sequence 1. toggle position 1 [11:0] and toggle position 2 [23:12]. 23 [23:0] ffffff clpobtog_2 sequence 2. toggle position 1 [11:0] and toggle position 2 [23:12]. 24 [23:0] ffffff 0 clpobtog_3 clpobscp0 sequence 3. toggle position 1 [11: 0] and toggle position 2 [23:12]. clpob sequence-change position 0 (hard-coded to 0). 25 [7:0] 0 clpobsptr clpob sequence pointers for region 0 [1:0], 1 [3:2], 2[5:4], 3[7:6]. 26 [11:0] fff clpobscp1 clpob sequence-change position 1. 27 [11:0] fff clpobscp2 clpob sequence-change position 2. 28 [11:0] fff clpobscp3 clpob sequence-change position 3. table 11. pblk register map address data bit con- tent default value (hex) name description 30 [3:0] f pblkpol start polarities for pblk sequences 0, 1, 2, and 3. 31 [23:0] ffffff pblktog_0 sequence 0. toggle po sition 1 [11:0] and toggle position 2 [23:12]. 32 [23:0] ffffff pblktog_1 sequence 1. toggle po sition 1 [11:0] and toggle position 2 [23:12]. 33 [23:0] ffffff pblktog_2 sequence 2. toggle po sition 1 [11:0] and toggle position 2 [23:12]. 34 [23:0] ffffff 0 pblktog_3 pblkscp0 sequence 3. toggle position 1 [11: 0] and toggle position 2 [23:12]. pblk sequence-change positi on 0 (hard-coded to 0). 35 [7:0] 0 pblksptr pblk se quence pointers for region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. 36 [11:0] fff pblkscp1 pblk sequence-change position 1. 37 [11:0] fff pblkscp2 pblk sequence-change position 2. 38 [11:0] fff pblkscp3 pblk sequence-change position 3.
ad9949 rev. b | page 16 of 36 table 12. hblk register map address data bit content default value (hex) name description 40 [0] 0 hblkdir hblk internal/external. 0 = internal. 1 = external. 41 [0] 0 hblkpol hblk external active polarity. 0 = active low. 1 = active high. 42 [0] 1 hblkextmask hblk external masking polarity. 0 = mask h1 low. 1 = mask h1high. 43 [3:0] f hblkmask hblk internal masking polarity for each sequence 0 to 3. 0 = mask h1 low. 1 = mask h1 high. 44 [23:0] ffffff hblktog12_0 sequence 0. toggle position 1 [11:0] and toggle position 2 [23:12]. 45 [23:0] ffffff hblktog34_0 sequence 0. toggle position 3 [11:0] and toggle position 4 [23:12]. 46 [23:0] ffffff hblktog56_0 sequence 0. toggle position 5 [11:0] and toggle position 6 [23:12]. 47 [23:0] ffffff hblktog12_1 sequence 1. toggle position 1 [11:0] and toggle position 2 [23:12]. 48 [23:0] ffffff hblktog34_1 sequence 1. toggle position 3 [11:0] and toggle position 4 [23:12]. 49 [23:0] ffffff hblktog56_1 sequence 1. toggle position 5 [11:0] and toggle position 6 [23:12]. 4a [23:0] ffffff hblktog12_2 sequence 2. toggle position 1 [11:0] and toggle position 2 [23:12]. 4b [23:0] ffffff hblktog34_2 sequence 2. toggle position 3 [11:0] and toggle position 4 [23:12]. 4c [23:0] ffffff hblktog56_2 sequence 2. toggle position 5 [11:0] and toggle position 6 [23:12]. 4d [23:0] ffffff hblktog12_3 sequence 3. toggle position 1 [11:0] and toggle position 2 [23:12]. 4e [23:0] ffffff hblktog34_3 sequence 3. toggle position 3 [11:0] and toggle position 4 [23:12]. 4f [23:0] ffffff 0 hblktog56_3 hblkscp0 sequence 3. toggle position 5 [11: 0] and toggle position 6[23:12]. hblk sequence-change positi on 0 (hard-coded to 0). 50 [7:0] 0 hblksptr hblk se quence pointers for region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. 51 [11:0] fff hblkscp1 hblk sequence-change position 1. 52 [11:0] fff hblkscp2 hblk sequence-change position 2. 53 [11:0] fff hblkscp3 hblk sequence-change position 3. table 13. h1 to h2, rg, shp, shd register map address data bit content default value name description 60 [12:0] 01001 h1control h1 signal control. polarity [0](0 = inversion, 1 = no inversion). h1 positive edge location [6:1]. h1 negative edge location [12:7]. 61 [12:0] 00801 rgcontrol rg signal control. polarity [0](0 = inversion, 1 = no inversion). rg positive edge location [6:1]. rg negative edge location [12:7]. 62 [14:0] 0 drvcontrol drive strength control for h1 [2:0], h2 [5:3], h3 [8:6], h4 [11:9], and rg [14:12]. drive current values: 0 = off, 1 = 4.3 ma, 2 = 8.6 ma, 3 = 12.9 ma, 4 = 17.2 ma, 5 = 21.5 ma, 6 = 25.8 ma, 7 = 30.1 ma. 63 [11:0] 00024 sampcontrol shp/shd sample control. shp sampli ng location [5:0]. shd sampling location [11:6]. 64 [5:0] 0 doutphase dout phase control.
ad9949 rev. b | page 17 of 36 table 14. afe operation register detail address data bit content default value name description 00 [1:0] 0 pwrdown 0 = normal operation. 1 = reference standby. 2/3 = total power-down [2] 1 clpenable 0 = disable ob clamp. 1 = enable ob clamp. [3] 0 clpspeed 0 = select normal ob clamp settling. 1 = select fast ob clamp settling. [4] 0 fastupdate 0 = ignore vga update. 1 = very fast clamping when vga is updated. [5] 0 pblk_lvl dout value during pblk. 0 = blank to zero. 1 = blank to clamp level. [7:6] 0 test mode test operation only. set to zero. [8] 0 dcbyp 0 = enable dc restore circuit. 1 = bypass dc restore circuit during pblk. [9] 0 testmode test ope ration only. set to zero. [11:10] 0 cdsgain adjustment of cds gain. 0 = 0 db. 01 = ?2 db. 10 = ?4 db. 11 = 0 db. table 15. afe control register detail address data bit content default value name description 03 [1:0] 0 colorsteer 0 = off. 1 = progressive. 2 = interlaced. 3 = three field. [2] 1 pxgaenable 0 = disable pxga. 1 = enable pxga. [3] 0 doutdisable 0 = data outputs are driven. 1 = data outputs are three-stated. [4] 0 doutlatch 0 = latch data outputs with dout phase. 1 = output latch transparent. [5] 0 grayencode 0 = binary encode data outputs. 1 = gray encode data outputs.
ad9949 rev. b | page 18 of 36 precision timing high spe e d timing ge nera tion the ad9949 g e n e ra t e s f l exi b le hig h s p ee d timin g sig n als usin g th e pr e c i s i o n t i m i n g co r e . this co r e is th e f o u n da tio n f o r g e n e r - a t in g t h e t i min g us e d fo r b o t h t h e c c d and t h e afe: t h e r e s e t ga t e (r g), h o r i zo n t al dr i v er s (h1 t o h4), a nd t h e s h p/s h d s a m p le c l o c ks. a uniq ue a r c h i t ec t u r e mak e s i t r o u t ine f o r th e sys t em desig n er t o o p t i mi ze ima g e qual i t y b y p r o v i d in g p r e c is e co n t r o l o v er t h e h o r i zo n t a l c c d r e ado u t and t h e afe co r r e- la t e d dou b le s a m p ling. timing resolution the pr e c is io n t i m i n g co r e us es a 1 mas t er c l o c k in p u t (cli) as a r e fer e n c e. thi s clo c k sh o u ld b e t h e s a m e as t h e c c d pixel c l oc k f r eq ue n c y . f i gur e 16 ill u s t ra t e s h o w t h e in t e rn al ti mi n g co r e d i v i d e s th e m a s t e r c l oc k peri od in t o 48 s t eps o r ed g e p o s i t i ons . t h e r e f ore, t h e e d g e re s o lut i on of t h e pr e c is io n t i m i n g co r e is (t cli /48). f o r m o r e info r m a t io n on using t h e cli i n p u t, r e fer t o t h e a p plica t io n s i n fo r m a t io n s e c t ion. high spee d clock pr ogrammability f i gu r e 17 sh o w s h o w t h e h i g h sp e e d clo c k s , rg, h1 t o h4, s h p , a n d s h d , a r e g e nera t e d. the rg p u l s e has p r og ra mma- b l e rising a n d fa l l i n g ed g e s a n d m a y be i n v e rt ed u s i n g th e p o la r i ty co n t r o l. the h o r i zon t a l clo c ks h1 and h3 ha ve p r og r a m mabl e r isin g a nd fa l l i ng e d ges an d p o l a r i ty co n t r o l. th e h2 an d h4 c l o c ks a r e al wa ys in v e rs es o f h 1 a nd h3, r e - sp e c t i v e ly . t a bl e 1 6 su mmar i ze s t h e hig h sp e e d t i mi ng re g i ste r s a n d t h eir p a ramet e r s . e a c h edg e lo ca tio n s e t t in g is 6 b i ts wide , b u t o n ly 48 valid e d g e lo ca t i on s a r e a v a i la b l e . th er efo r e , t h e reg i s t er v a l u es a r e ma p p e d in t o f o ur q u adran t s, wi th e a c h q u ad ra n t co n t a i ni n g 12 edg e lo c a tion s. t a b l e 17 sh o w s the co r r ec t r e g i s t er val u es f o r t h e co r r es p o ndi n g e d g e lo ca t i on s. notes 1. pixel clock period is divided into 48 positions, providing fine edge resolution for high speed clocks. 2. there is a fixed delay from the cli input to the internal pixel period positions ( t clidly = 6 ns typ). p[0] p[48] = p[0] p[12] p[24] p[36] 1 pixel period ... ... cli t clidly position 03751-017 f i gure 1 6 . hi gh speed clo c k res o l u t i on fr om cli ma ste r cl oc k input h1/h3 h2/h4 ccd signal rg 12 3 4 56 programmable clock positions: 1. rg rising edge. 2. rg falling edge. 3. shp sample location. 4. shd sample location. 5. h1/h3 rising edge position6. h1/h3 falling edge position (h2/h4 are inverse of h1/h3). 03751-018 f i g u re 17. h i g h spe e d cl ock prog r a m m ab le l o c a t i o n s
ad9949 rev. b | page 19 of 36 table 16. h1c o ntr o l, rg contr o l, d r vcon tr o l , and sampco ntrol register parameters parameter length range description polarity 1b high/low polari ty control for h1/h3 and rg ( 0 = no inversion, 1 = inversi o n ) . positive edge 6b 0 to 47 ed ge location positive edge location for h1/h 3 and rg. negative edge 6b 0 to 47 ed ge location negative edge l o cation for h1/h3 and rg. sample location 6b 0 to 47 sample location sampling location for shp and shd. drive control 3b 0 to 7 current s t eps drive current fo r h1 to h4 and r g outputs, 0 to 7 steps of 4.1 ma each. dout phase 6b 0 to 47 ed ge loca tion phase location of data outp uts with respect to pix e l period. table 17. preci sion timing edge locations quadrant edge location (decimal) register val u e (decimal) register val u e (binary) i 0 to 11 0 to 11 000000 to 0010 11 ii 12 to 23 16 to 27 010000 to 0110 11 iii 24 to 35 32 to 43 100000 to 1010 11 iv 36 to 47 48 to 59 110000 to 1110 11 h-driver a n d rg ou t p uts i n addi t i on t o t h e p r og ra mma ble t i mi n g p o si t i o n s, t h e ad994 9 fe a t ur es o n -chi p o u t p u t dr i v ers fo r t h e r g and h1 t o h4 o u t p u t s. t he s e dr i v ers a r e p o wer f u l en o u g h t o dir e c t l y dr i v e t h e c c d in pu ts. the h- dr i v er and r g dr i v er c u r r en t ca n b e ad j u s t e d fo r o p t i m u m r i se /fall t i m e i n t o a p a r t i c u l a r lo ad b y usin g t h e dr v c o n tr o l r e g i s t er (a ddr es s 062) . the d r v c ontr o l r e g i s t er i s divide d in t o f i v e dif f e r- en t 3-b i t val u es, eac h on e bein g ad j u s t ab le in 4. 1 ma in cr em en ts . th e minim u m s e t t in g o f 0 is eq ual t o o ff o r thr e e-s t a t e , and th e m a xi - m u m s e t t in g o f 7 is eq ual t o 30.1 ma. a s s h o w n i n fi g u re 1 8 , t h e h 2 / h 4 output s are i n ve r s e s of h 1 / h 3 . t h e i n te r n a l prop ag a t i o n d e l a y re su lt i n g f r om t h e s i g n a l i n ve r s io n is less t h a n l ns, w h ich is sig n if ican t l y less t h an t h e ty p i c a l r i s e t i m e dr iving t h e c c d lo ad . this r e su l t s in a h1/ h 2 cr oss o v e r vol t age a t a p - pro x i m a t ely 5 0 % of t h e out p ut s w i n g . t h e c r o s s o ve r vol t age i s not pro g r a mmabl e. digi tal da ta ou tpu t s the ad9949 da ta o u t p u t p h as e is p r og ra mma b l e usin g t h e d o utp h as e r e g i s t er (a ddr e s s 0 64). an y edg e f r o m 0 t o 47 ma y be p r o- g r a m m e d , as sho w n i n f i gur e 1 9 . the p i p e l i n e dela y fo r t h e dig i t a l d a t a o u t p u t is sho w n i n f i g u r e 20. fixed crossover voltage h1/h3 h2/h4 t pd h2/h4 h1/h3 t rise t pd << t rise 03751-019 f i g u re 18. h- cl ock i n vers e p h as e r e l a t i ons h ip
ad9949 rev. b | page 20 of 36 notes 1. digital output data (dout) phase is adjustable with respect to the pixel period. 2. within one clock period, the data transition can be programmed to any of the 48 locations. p[0] p[48] = p[0] cli 1 pixel period p[12] p[24] p[36] dout t od 03751-020 f i gure 1 9 . di g i ta l o u tput p h a s e a d justm e nt notes 1. default timing values are shown: shdloc = 0, dout phase = 0. 2. higher values of shd and/or doutphase will shift dout transition to the right, with respect to cli location. dout ccdin cli shd (internal) n n + 1 n + 2 n + 12 n + 11 n + 10 n + 9 n + 8 n + 7 n + 6 n + 5 n + 4 n + 3 n + 13 n ? 13 n? 3 n? 4 n? 5 n? 6 n? 7 n? 8 n? 9 n ? 10 n ? 11 n ? 12 n? 2 n? 1 n + 1 n sample pixel n n? 1 03751-021 t clidly pipeline latency = 11 cycles f i gure 20. p i pel i ne d e lay f o r d i git a l d a ta o u tput
ad9949 rev. b | page 21 of 36 horizontal clamping and blanki ng the ad9949 s ho r i zo n t al c l am p i n g an d b l anking p u ls es a r e f u l l y p r og ra mma b l e to sui t a va r i e t y o f a p plica t io n s . i ndivi d u a l s e q u e n ces a r e def i n e d fo r e a ch sig n al , w h ich a r e t h en o r ga ni ze d in t o m u l t i p le r e g i o n s d u r i n g im a g e r e ado u t. t h is a l lo ws t h e da r k p i xel clam p i n g and b l an k i n g p a tter n s to b e cha n ge d a t e a ch s t a g e o f t h e r e ado u t t o acc o mm o d a t e dif f er en t ima g e t r a n sfer t i min g a nd hig h sp e e d line sh if ts. individual clpob and pblk sequ ences the af e h o r i zon t a l t i mi n g co nsists o f clpob a nd pblk, as sho w n i n f i gur e 21. th e s e tw o sig n a l s a r e i n de p e nden t ly p r og ra mm e d usin g t h e p a ram e ters s h o w n i n t a b l e 18. th e st a r t po l a ri t y , f i r s t t o ggl e pos i ti o n , a n d sec o n d t o ggl e pos i ti o n a r e f u ll y p r ogra mma b l e f o r eac h sig n al . th e clpob a n d p b lk sig n als a r e ac ti ve lo w an d sh o u ld b e p r og ra mme d acco r d in g l y . u p t o f o ur in divid u al s e q u en ces ca n be cr e a t e d f o r eac h sig n al . individual hblk sequ ences the hblk p r o g ra mma b l e t i mi n g sh o w n in f i g u r e 22 is simi la r t o clpo b an d p b l k . h o we v e r , t h er e is n o s t a r t p o la r i ty co n t r o l . on ly t h e tog g l e p o si t i ons ar e us e d to desig n a t e t h e s t a r t a nd t h e st op p o si tio n s o f t h e bla n kin g p e r i o d . a d di tio n al l y , t h er e is a p o la r i t y co n t r o l , hbl k mas k , w h ich desig n a t es t h e p o la r i ty o f th e ho r i zo n t al c l o c k sig n als h1 t o h 4 d u r i n g t h e b l a n k i n g p e r i o d . s e t t in g h b l k mas k hig h s e ts h1 = h3 = lo w a nd h2 = h4 = hig h d u r i n g t h e b l a n k i ng, as s h o w n in f i g u r e 23. u p to fou r i n d i v i d u a l s e qu e n c e s are a v ai l a bl e for h b l k . 3 2 1 hd clpob pblk programmable settings: 1. start polarity (clamp and blank region are active low). 2. first toggle position. 3. second toggle position. active active 03751-022 ... ... f i gure 21. cl amp a n d p r ebl a nk p u ls e p l acem ent 2 1 hd hbl k programmable settings: 1. first toggle position = start of blanking. 2. second toggle position = end of blanking. blank blank 03751-023 ... ... f i gure 22. hor i zont al blank i ng ( h bl k ) p u lse p l acement table 18. c l pob and pblk indiv i dual seq u ence paramet e rs parameter length range description polarity 1b high/low starting polarity of clamp and pblk pulses for s e quences 0 to 3. toggle position 1 12b 0 to 4095 pixe l location first toggle posi tion wi thin the line for sequences 0 to 3. toggle position 2 12b 0 to 4095 pixel location second toggle position within t h e line for sequences 0 to 3. ta ble 19. hbl k in di vi dua l s e quence pa ra m e t e rs parameter length range description hblkmask 1b high/low masking polarity for h1 for seq u ences 0 to 3 (0 = h1 low, 1 = h1 high). toggle position 1 12b 0 to 4095 pixel location first toggle posi tion with in the line for sequences 0 to 3. toggle position 2 12b 0 to 4095 pixel location second toggle position with in t h e line for sequences 0 to 3. toggle position 3 12b 0 to 4095 pixel location third toggle po sition within the line for sequences 0 to 3. toggle position 4 12b 0 to 4095 pixel location fourth toggle p o sition with i n the line for sequences 0 to 3. toggle position 5 12b 0 to 4095 pixel location fifth to ggle position within the line for sequences 0 to 3. toggle position 6 12b 0 to 4095 pixel location sixth to ggle position within the line for sequences 0 to 3.
ad9949 rev. b | page 22 of 36 hd hbl k the polarity of h1 during blanking is programmable (h2 is opposite polarity of h1). h1 / h 3 h1 / h 3 h2 / h 4 ... ... ... ... 03751-024 f i gure 2 3 . h b l k m a sk i n g c o ntrol hblk special h-blank pattern is created using multiple hblk toggle positions. h1/h3 h2/h4 tog1 tog2 tog3 tog4 tog5 tog6 03751-025 f i g u re 24. gen e r a t i ng spec ia l hbl k p a t t erns ta ble 20. hori zont a l seque nce cont rol pa ra meters for c l pob, pblk, a n d hblk r e g i s t e r l e n g t h r a n g e d e s c r i p t i o n scp 12b 0 to 4095 line number clob/pblk/hblk scp to define horizontal regi ons 0 to 3. sptr 2b 0 to 3 sequence number sequence point e r for horizontal regions 0 to 3.
ad9949 rev. b | page 23 of 36 gene rating s p eci a l hblk patterns s i x t o g g l e p o si t i o n s a r e a v a i lab l e fo r hb lk. n o r m al l y , o n l y tw o of t h e to g g l e p o s i t i ons are u s e d to ge ne r a te t h e st a ndard h b l k i n t e r v a l . h o w e v e r , th e add i ti o n al t o ggle posi ti o n s m a y be use d t o g e n e ra t e sp ec ial h b l k p a t t er n s , as sh o w n in f i gur e 24. th e p a t t er n i n t h is e x a m ple us es al l six t o g g l e p o si t i o n s t o g e n e r a t e tw o ext r a g r o u ps o f p u ls es d u r i n g t h e hblk in t e r v al . by cha n g i n g t h e t o g g l e p o si t i o n s, dif f er en t p a t t er n s can b e cr e a t e d . horizontal sequence control the ad9949 us es s e q u en ce c h an g e p o si tio n s (s cp) a nd s e q u e n ce p o in te rs (s ptr) to o r ga niz e t h e i ndiv i d u a l h o r i zon t a l s e q u en ces. u p to f o ur scp s a r e a v a i la b l e t o divide t h e r e ado u t in t o f o ur s e p a ra t e r e g i o n s, as sho w n in f i gur e 2 5 . the scp0 is al wa ys ha r d -co d ed t o l i n e 0, and scp1 t o scp 3 a r e r e g i s t er p r o g r a mma b l e. d u r i n g e a ch r e g i o n b o u n de d b y t h e s c p , t h e s p tr r e g i s t ers desig n a t e whic h s e q u e n ce is us e d b y e a ch sig n a l . clpo b , pb lk, a nd hb l k e a ch ha v e a s e p a ra te s e t o f scp s . f o r exa m ple , clpobscp1 def i n e s reg i on 0 fo r clpo b , a nd in t h a t re g i on a n y of t h e f o u r i n d i v i du a l c l p o b s e qu e n c e s m a y b e s e le c t e d wi t h t h e clpo bs p t r r e g i s t er . th e n e xt scp def i n e s a n e w r e gi o n a n d i n tha t r e gi o n , ea c h s i gn al c a n be a s s i g n ed t o a dif f er en t i ndivi d u al s e q u e n c e . the s e q u e n ce c o n t r o l r e g i s t ers a r e s u mma r i ze d in t a b l e 20. external h b lk signal the ad9949 can als o b e us ed wi th an ext e r n al hb lk s i g n al . s e t t in g t h e hbl k d i r r e g i s t er ( a ddr es s 040) to hig h dis a b l es t h e in t e r n al h b lk sig n al g e n e r a t i o n . th e p o la r i ty o f t h e ext e r - na l sig n a l is sp e c if ie d usin g t h e hblk pol r e g i st er , an d t h e mask i n g p o la r i t y o f h1 is sp e c if ie d usin g t h e h b lkmask r e g i s t er . t a b l e 2 1 s u mma r i zes t h e r e g i st er val u es w h en usin g an ext e rn al hb lk si gn al . up to four individual horizontal clamp and blanking regions may be programmed within a single field, using the sequence change positions. sequence change of position 1 sequence change of position 2 sequence change of position 3 single field (1 vd interval) clamp and pblk sequence region 0 sequence change of position 0 (v-counter = 0) clamp and pblk sequence region 3 clamp and pblk sequence region 2 clamp and pblk sequence region 1 03751-026 f i g u re 25. cl amp a n d bl ank i ng s e q u e n c e f l ex ib il it y table 21. e x ternal hblk regi ster parameters register length range description hblkdir 1b high/low specifies hblk i n ternally gene r a ted or externall y supplied. 1 = external. hblkpol 1b high/low external hblk a c tive polarity. 0 = active low. 1 = active high. hblkextma s k 1b high/low external hblk masking polarity. 0 = mask h1 low. 1 = mask h1 high.
ad9949 rev. b | page 24 of 36 h-counter synchr oni z ation the h- c o u n t e r r e s e t o c c u rs s e v e n cli c y cles f o l l o w in g t h e h d fal l ing e d g e . the pxga st e e r i n g is sy n c hr o n i z e d w i t h t h e r e s e t o f th e i n te r n a l h - c o u n te r ( s e e fi g u re 2 6 ) . a s m e n t ion e d in t h e h - c o u n t e r b e ha vio r s e c t io n, t h e ad9949 h-co un t e r r o l l s o v er t o zer o a nd co n t in ues co u n ting w h en t h e maxim u m co un t e r len g t h is exceeded . th e n e w e r ad9949 a p r o d uc t do es n o t r o l l o v er b u t h o lds a t i t s maxim u m val u e u n til t h e n e xt h d r i sin g edg e oc cu r s . 000 1 1 2 111 0 0 3 11 00 0123456789 1 0 1 1 1 2 1 4 1 5 0123 02 h-counter reset vd notes 1. internal h-counter is reset 7 cli cycles after the hd falling edge (when using vdhdedge = 0). 2. typical timing relationship: cli rising edge is coincident with hd falling edge. 3. pxga steering is syncronized with the reset of the internal h-counter (mosaic separate mode is shown). hd xx xx x x x pxga gain register cli 3 xx xx x x x h-counter (pixel counter) x x x x x x 03751-027 f i gure 26. h- cou n ter s y nch r oni z at ion
ad9949 rev. b | page 25 of 36 powe r -up proce dure recommended power-up sequence w h en t h e ad9 949 is p o w e r e d u p , t h e f o l l o w ing s e q u en ce is r e co mm e nde d ( r efer t o f i gur e 27 fo r e a ch s t ep): 1. t u r n o n t h e p o w e r s u p p lies f o r th e ad9949. 2. a p pl y t h e mast e r c l o c k in pu t, c l i, vd , an d hd . 3. al t h o u g h t h e ad9949 co n t ain s a n o n -chi p , p o w e r - o n r e s e t, a s o f t w a re re s e t of t h e i n t e r n a l re g i ste r s i s re c o m m e n d e d. w r i t e a 1 t o t h e sw_r s t r e g i s t er (a ddr es s 01 0 ), w h ich r e s e ts t h e i n ter n a l r e g i st ers t o t h eir defa u l t va l u e s . this b i t is s e lf-c le a r in g and a u t o ma tical l y r e s e ts bac k t o 0. 4. the pr e c is io n t i m i n g c o re m u st b e re s e t b y w r it i n g a 0 to th e t g core_ r s t b r e g i s t er ( a ddr es s 012) f o l l o w ed b y wr i t ing a l to t h e tg c o r e _ r stb re g i ste r . thi s st ar ts t h e in t e r n a l t i m i n g co r e o p era t io n . 5. w r i t e a 1 t o t h e p r e v e n tupd a t e r e g i s t er (a ddr es s 014). this p r e v en ts t h e u p da t i n g o f t h e s e r i al r e g i s t er da ta . 6. w r i t e t o t h e desir e d r e g i s t ers t o co nf igur e hig h sp e e d t i mi n g an d h o r i zo n t a l t i ming. 7. w r i t e a 1 t o the o u t_ co ntro l r e g i s t er (a ddr e s s 011). t h i s allo w s th e o u t p u t s t o b e co m e acti v e a f t e r th e n e xt vd/h d r i sin g e d g e . 8. w r i t e a 0 t o t h e p r e v e n tupd a t e r e g i s t er (a ddr es s 014). this a l lo ws t h e s e r i a l info r m a t io n t o b e u p da te d a t n e xt v d /h d fa l l in g edge . 9. the n e xt vd /h d fal l ing e d g e a l lo ws r e g i s t er up da t e s t o o c c u r , i n cl ud ing out_ c o n t rol, w h ich enab les a l l clo c k output s . vdd (input) serial writes vd (output) 1h odd field even field ... ... digital outputs clocks active when out_control register is updated at vd/hd edge h1/h3, rg h2/h4 t pwr cli (input) hd (output) 1v ... ... 03751-028 1 2 2 3 4 5 6 7 8 9 f i gure 27. r e c o m m e nded p o wer - up s e quence
ad9949 rev. b | page 26 of 36 analog front e n d descri ption a nd ope ration the ad9949 s i g n al p r o c es sin g c h a i n is sh o w n in f i gur e 28. e a ch p r o c es si n g s t ep is es s e n t ial in achie v i n g a hig h q u ali t y ima g e f r o m t h e ra w c c d p i xe l da t a . dc restore t o r e d u ce t h e l a rg e dc o f fs et o f th e c c d o u t p ut sig n al , a dc r e s t o r e cir c ui t is us ed wi t h a n ex t e r n al 0.1 f s e r i es co u p lin g ca p a ci t o r . this res t o r es the dc le v e l o f the c c d sig n al t o ap p r ox i m at e l y 1 . 5 v t o b e c o mp at i b l e w i t h t h e 3 v s u p p l y v o l t a g e o f t h e ad9949. correlated double sampler the cds c i r c ui t s a m p les e a ch c c d p i xe l t w ic e t o ext r ac t t h e v i d e o i n for m a t i o n an d re j e c t l o w f r e q u e nc y noi s e. t h e t i m i ng s h o w n in f i gur e 17 ill u s t ra t e s h o w t h e t w o in t e rn all y g e n e ra t e d cds clo c ks, s h p a nd s h d , a r e us e d t o s a m p le t h e r e fer e n c e l e vel and t h e c c d s i g n a l l e vel, re sp e c t i v e ly . t h e pl ac e m e n t of t h e s h p and shd s a m p l i n g e d ges is deter m i n e d b y t h e s e t t i n g o f t h e sa mpc o ntr o l r e g i ster lo ca t e d a t a d dr es s 063. place m e n t o f t h es e t w o clo c k si g n a l s is cr i t ica l i n achi e v in g t h e b e st p e r f or m a n c e f r om t h e c c d . the ga i n i n t h e cds is f i xe d a t 0 db b y defa u l t. u s in g bi ts d10 a nd d11 i n t h e afe o p era t ion r e g i s t er , t h e ga i n ma y b e r e d u c e d t o ?2 db o r ?4 db . this al lo ws th e ad9949 t o accep t an in p u t s i gn al o f gr ea t e r th a n 1 v p - p . s e e t a b l e 1 4 f o r r e gi s t e r d e ta il s . tab l e 22. a d justab le cds gai n operation regi ster bits d11 d10 cds ga in max cds input 0 0 0 db 1.0 v p-p 0 1 ?2 db 1.2 v p-p 1 0 ?4 db 1.6 v p-p 1 1 0 db 1.0 v p-p pxga the pxga p r o v ides s e p a ra t e gain ad j u s t m e n t fo r t h e i ndivi d u a l co lo r p i x e ls. a p r ogra mma b l e ga in am p l if ier wi th f o ur sep a ra t e val u es, t h e pxg a has t h e c a p a b i li ty t o m u l t i p le x i t s ga in val u e o n a p i xe l - t o -p ixe l basis (s e e f i gur e 29). this a l lo ws lo w e r o u t p u t colo r p i xe ls t o be gain ed u p t o ma t c h hig h er o u t p u t color p i xe ls. als o , the pxga ma y be us e d t o ad j u st t h e colo rs f o r whi t e bala n c e , r e d u ci n g the a m o u n t o f di gi tal p r oce s s i n g tha t is n e e d e d . the fo ur dif f er en t ga in val u es a r e s w i t ch e d acco r d in g t o t h e colo r s t e e r i n g cir c ui t r y . thr e e dif f er en t c o lo r s t e e r i n g m o des fo r dif f er en t typ e s o f c c d colo r f i l t er a rra ys a r e p r og ra mma b l e i n t h e afe c t l m o d e r e g i s t er a t a d dr es s 003 (s ee f i gur e 33 to f i gur e 35 f o r timin g exa m p l es ). f o r exa m p l e , p r o g re ss ive ste e r i ng mo de ac c o mmo da te s t h e p o p u l a r b a ye r a r ra n g e m en t o f r e d , gr ee n , a n d b l ue f i l t e r s (see f i gur e 30). 6db ~ 42db ccdin digital filter clpob dc restore optical black clamp 12-bit adc vga dac 8 cds internal vref 2v full scale 0db ~ 18db shp shd pxga 1.5v output data latch reft refb dout phase shp shd dout phase clpob pblk pblk 1.0v 2.0v dout ad9949 0db, ?2db, ? 4db 1.0 f 1.0 f 1.0 f 03751-029 pxga gain registers vga gain register clamp level register 12 v-h timing generation precision timing generation f i g u re 28. a n a l og f r ont e n d f u nc t i on a l b l o c k d i ag r a m
ad9949 rev. b | page 27 of 36 color steering control 4:1 mux gain0 gain1 gain2 gain3 pxga pxga steering mode selection vd hd pxga gain registers control register bits d0 to d1 shp/shd vga cds 03751-030 8 4:1 mux 2 3 f i g u re 29. px g a b l o c k d i ag r a m line0 gain0, gain1, gain0, gain1, ... r r gr gr line1 line2 gain2, gain3, gain2, gain3, ... gain0, gain1, gain0, gain1, ... color steering mode: progressive r rg r gr gb b ccd: progressive bayer gb b gb b gb b 03751-031 f i gure 30. c c d co l o r f i lter e x a m pl e p r og r e s s i ve s c an the s a m e b a yer p a t t er n can a l s o b e i n ter l ace d , a nd t h e in t e rlac ed m o de sh o u ld be us e d wi t h this typ e o f c c d (s ee f i g u r e 3 1 ) . t h e c o l o r s t ee ri n g p e rf o r m s th e p r o p e r m u l t i p l e xi n g o f th e r , g, an d b ga in va l u es (lo a ded in t o t h e pxga ga in r e g i s t ers) a nd is syn c hr o n i z e d b y t h e us er wi t h v e r t ical (vd) a nd h o r i zon t a l ( h d) sy n c p u ls es. f o r t i min g info r m a t io n, s e e f i gur e 34. line0 gain0, gain1, gain0, gain1, ... rr g r gr line1 line2 gain0, gain1, gain0, gain1, ... gain0, gain1, gain0, gain1, ... gb gb bb line0 gain2, gain3, gain2, gain3, ... line1 line2 gain2, gain3, gain2, gain3, ... gain2, gain3, gain2, gain3, ... color steering mode: interlaced gb gb bb gb gb bb gb gb bb rr g r gr rr g r gr rr g r gr even field odd field ccd: interlaced bayer 03751-032 f i gure 31. c c d co l o r f i lter e x a m pl e inter l a c ed r e ad out a t h ird ty p e o f r e ado u t us es t h e b a yer p a t t er n divide d i n to t h r e e dif f er en t r e ado u t f i elds. t h e 3 - f i eld m o de sh o u l d b e us e d w i t h this typ e o f c c d (s ee f i gur e 3 2 ). the colo r s t eer i n g p e r f o r m s t h e p r op er m u l t i p lexin g o f t h e r , g, an d b gai n val u es (lo a de d in t o t h e pxga g a in r e g i st ers) a nd is sy n c hr o n i z e d b y t h e us er wi th v e r t ic al (v d) a nd h o r i zon t al (hd) sy n c p u ls es. f o r timing info r m a t io n, s e e f i gur e 35. line0 gain0, gain1, gain0, gain1, ... r gr line1 line2 gain2, gain3, gain2, gain3, ... gain0, gain1, gain0, gain1, ... line0 gain2, gain3, gain2, gain3, ... line1 line2 gain0, gain1, gain0, gain1, ... gain2, gain3, gain2, gain3, ... color steering mode: three field gb b gb b r gr first field second field ccd: 3-field readout line0 gain0, gain1, gain0, gain1, ... r gr line1 line2 gain2, gain3, gain2, gain3, ... gain0, gain1, gain0, gain1, ... r gr third field gb b gb b r gr r gr gb b r gb gb r r r gb gb r r gb gb gb b gr b b gr gr gr b b gr gr b b 03751-033 f i gu r e 3 2 . c c d c o lo r f i l t e r ex am ple t h r ee-f i el d rea d o u t
ad9949 rev. b | page 28 of 36 220 33 1 1 vd notes 1. vd falling edge will reset the pxga gain register steering to 0101 line. 2. hd falling edges will alternate the pxga gain register steering between 0101 and 2323 lines. 3. fieldval is always reset to 0 on vd falling edges. hd 11 0 x x pxga gain register fieldval 0 fieldval = 0 02 2 0 33 1 1 11 0 00 0 fieldval = 0 03751-034 f i gure 33. pxg a co l o r s t ee ring p rogres s i ve mod e 00 3 11 2 2 vd notes 1. fieldval = 0 (start of first field) will reset the pxga gain register steering to 0101 line. 2. fieldval = 1 (start of second field) will reset the pxga gain register steering to 2323 line. 3. hd falling edges will reset the pxga gain register steering to either 0 (fieldval = 0) or 2 (fieldval = 1). 4. fieldval will toggle between 0 and 1 on each vd falling edge. hd 11 0 x x pxga gain register fieldval 0 fieldval = 0 31 1 00 0 0 33 2 21 fieldval = 1 fieldval = 0 1 03751-035 f i gure 34. pxg a co l o r s t ee ring interl a c e d m o de 22 3 33 2 2 vd notes 1. fieldval = 0 (start of first field) will reset the pxga gain register steering to 0101 line. 2. fieldval = 1 (start of second field) will reset the pxga gain register steering to 2323 line. 3. fieldval = 2 (start of third field) will reset the pxga gain register steering to 0101 line. 4. hd falling edges will alternate the pxga gain register steering between 0101 and 2323 lines. 5. fieldval will increment at each vd falling edge, repeating the 0...1...2...0...1...2 pattern. hd 11 0 x x pxga gain register fieldval 0 fieldval = 0 31 1 00 2 2 00 1 13 fieldval = 1 fieldval = 2 3 03751-036 f i gure 35. pxg a co l o r s t ee ring t hre e -f ie ld mod e
ad9949 rev. b | page 29 of 36 the pxga ga in f o r e a c h o f th e f o ur c h a nne ls is va r i ab le f r o m 0 db t o 18 db in 512 s t eps, s p ecif ied usin g t h e p x ga gai n 01 a nd pxga g a i n 23 r e g i s t ers. th e pxg a ga in c u r v e is s h o w n i n figure 36. the pxga gain01 register contains nine bits each for pxga gain0 and gain1, and the pxga gain23 register contains nine bits each for pxga gain2 and gain3. pxga gain register code 18 0 pxga gain (db) 64 128 192 256 320 384 448 511 15 12 9 6 3 0 03751-037 figure 36. pxga gain curve variable gain amplifier the vga stage provides a gain range of 6 db to 42 db, pro- grammable with 10-bit resolution through the serial digital interface. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. when com- pared to 1 v full-scale systems, the equivalent gain range is 0 db to 36 db. the vga gain curve follows a linear-in-db characteristic. the exact vga gain can be calculated for any gain register value by using the equation gain (db) = (0.0351 code) + 6 db where the code range is 0 to 1023. there is a restriction on the maximum amount of gain that can be applied to the signal. the pxga can add as much as 18 db, and the vga is capable of providing up to 42 db. however, the maximum total gain from the pxga and vga is restricted to 42 db. if the registers are programmed to specify a total gain higher than 42 db, the total gain is clipped at 42 db. adc the ad9949 uses a high performance adc architecture, optimized for high speed and low power. dnl performance is typically better than 0.5 lsb. the adc uses a 2 v input range. see figure 9 and figure 10 for typical linearity and noise performance plots for the ad9949. 03751-038 vga gain register code 1023 0 127 255 383 511 639 767 895 vga gain (db) 42 36 30 24 18 12 0 figure 37. vga gain curve (pxga not included) optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccds black level. during the optical black (shielded) pixe l in- terval on each line, the adc output is compared with a fixed black level reference, selected by the user in the clamp level reg is- ter. the value can be programmed between 0 lsb and 255 lsb in 256 steps. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a dac. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during the postprocessing, the ad9949 optical black clamping may be disabled using bit d2 in the oprmode register. when the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment . the clpob pulse should be placed during the ccds optical black pixels. it is recommended that the clpob pulse duration be at least 20 pixels wide to minimize clamp noise. shorter pulse widths may be used, but clamp noise may increase and the ability to track low frequency variations in the black level will be reduced. see the horizontal clamping and blanking and applications information sections for timing examples. digital data outputs the ad9949 digital output data is latched using the dout phase register value, as shown in figure 28. output data timing is shown in figure 19 and figure 20. it is also possible to leave the output latches transparent, so that the data outputs are valid immediately from the adc. programming the afe control register bit d4 to a 1 sets the output latches transparent. the data outputs can also be disabled (three-stated) by setting the afe control register bit d3 to a 1. the data output coding is normally straight binary, but the coding may be changed to gray coding by setting the afe control register bit d5 to a 1.
ad9949 rev. b | page 30 of 36 appli c ations inf ormati o n circuit configuration the ad9949 r e co mm ende d circ ui t co nf igura t io n is sh o w n in f i gur e 38. a c hievin g g o o d imag e q u al i t y f r o m th e ad9949 r e q u ir es ca r e f u l a t t e n t io n t o pc b la yo u t . al l sig n als s h o u l d be r o u t e d t o main t a in lo w n o is e p e r f o r ma n c e . t h e c c d o u t p ut sig n al sh o u ld be dir e c t l y r o u t ed t o p i n 27 thr o u g h a 0.1 f ca p a ci t o r . th e mas t er c l o c k c l i s h o u l d be ca ref u l l y r o u t ed t o p i n 25 t o mi ni mi ze i n t e r f er ence w i t h t h e c c d i n, ref t , an d refb sig n als. the dig i t a l o u t p u t s an d c l o c k in p u ts a r e lo c a t e d o n p i n s 1 t o 13 a nd pin s 31 to 4 0 a nd sh o u ld b e co nn e c te d to t h e dig i t a l as ic a w a y f r o m t h e ana l og a nd c c d clo c k sig n a l s. placing s e r i es re s i stors cl o s e to t h e di g i t a l output pi ns ma y h e lp to re d u c e d i gi tal co d e tra n si ti o n n o ise . i f th e d i g i tal o u t p u t s m u s t d r i v e a lo ad la rg er tha n 20 pf , b u f f er in g is r e co mm ended t o minimize addi t i o n a l n o is e. i f t h e dig i t a l as i c ca n accep t gr a y co de , t h e ad9949 s o u t p u t s ca n be s e lec t ed t o o u t p u t da ta in g r a y c o de f o r m a t u s in g th e co n t r o l r e g i s t e r b i t d5. g r a y co din g h e l p s r e d u ce p o ten t ia l dig i t a l tr a n si tio n n o is e co m p a r e d wi t h b i na r y co din g . the h1C h 4 and rg t r aces sh ou ld ha ve lo w i n d u c t an ce t o a v oid e x c e ss ive d i s t or t i on of t h e s i g n a l s . h e av i e r t r a c e s are re c o m - m e nde d b e ca us e o f t h e la rge t r a n sien t c u r r e n t d e ma nd o n h1Ch4 f r o m t h e ca p a c i ti v e lo ad o f the c c d . i f p o s s i b le , p h ysical l y lo ca tin g t h e ad9949 c l os er t o th e c c d wil l r e d u ce t h e i n d u c t an ce o n t h es e l i n e s. a s alwa ys, t h e ro u t in g p a t h s h o u l d be as direc t as p o s s ib le f r o m the ad994 9 t o th e c c d . grounding and decoupling recommendations a s sho w n i n f i g u r e 38, a sin g le g r o u n d plan e is r e co mm e nde d f o r th e ad9949. this g r o u nd p l a n e sh o u ld be as co n t in uo us as p o s s i b le, p a r t ic u l a r l y a r o u nd p i n s 23 t o 30. this en s u r e s tha t al l a n alog de co u p lin g ca p a c i t o rs p r o v ide t h e lo w e s t p o s s i b le im p e dan c e p a t h b e tw e e n t h e p o w e r a nd b y p a ss p i n s and t h eir re sp e c t i ve g r ou n d pi ns . a l l h i g h f r e q u e nc y d e c o upl i ng c a p a c i tors s h ou l d b e l o c a te d a s cl o s e a s p o ss ibl e to t h e p a c k ag e p i n s . i t is r e co m m e nde d t h a t t h e ex p o s e d p a d d l e o n t h e b o t t o m o f t h e p a cka g e b e s o lder e d t o a l a rg e p a d , w i t h m u l t i p le v i as co nn e c t i n g t h e p a d to t h e g r o u nd plan e. al l t h e su p p ly p i n s m u st b e de c o u p le d to g r o u nd w i t h go o d q u al i t y , hig h f r eq uen c y c h i p ca p a ci t o rs. th er e sh o u ld als o be a 4 . 7 f or l a rge r b y p a ss c a p a c i tor for e a ch main su p p ly a v d d , r g vd d , hvdd , a nd d r vdd al t h o u g h t h is is n o t n e ce s s a r y fo r e a ch indivi d u a l p i n. i n m o st a p plic a t io n s , i t is e a sier t o sha r e t h e su p p ly fo r r g vdd an d hv dd , w h ich ma y b e done as lo n g as t h e i n d i v i d u a l su p p ly p i ns are s e p a r a tely b y p a ss e d . a s e p a r a te 3 v su p p ly ma y b e u s e d for dr v d d , b u t t h is s u p p ly p i n s h ou l d st i l l b e de co u p le d to t h e s a m e g r o u nd plan e as t h e r e st o f t h e ch i p . a s e p a r a te g r ou nd for dr v s s i s not re c o m m e n d e d. the r e f e r e n c e b y p a s s p i n s (reft , refb) sh o u l d b e deco u p le d t o g r o u n d as c l o s e as p o s s i b le t o th eir r e s p ec ti ve p i n s . the ana l o g i n put ( c c d i n ) c a p a c i tor shou l d a l s o b e l o c a te d cl o s e to th e p i n. 3v analog supply serial interface 3 ccd signal vd/hd/hblk inputs clp/blk output 4 3v driver s upply rg driver supply h driver supply master clock input 3v analog supply data outputs 12 h1 to h4 4 top view ad9949 pin 1 identifier 30 refb 29 reft 28 avss 27 ccdin 26 avdd 25 cli 24 tcvdd 23 tcvss 22 rgvdd 21 rg d1 1 d2 2 d3 3 d4 4 drvdd 6 d5 7 d6 8 d7 9 d8 10 40 d0 (lsb) 39 clp/pblk 38 hblk 37 dvdd 36 dvss 35 hd 34 vd 33 sck 32 sdi 31 sl d9 11 d1 0 12 (msb) d11 13 h1 14 h2 15 hvss 16 hvdd 17 h3 18 h4 19 rgvss 20 rg output + + + + drvss 5 4.7 f 0.1 f 0.1 f 4.7 f 4.7 f 0.1 f 0.1 f 4.7 f 0.1 f 0.1 f 1 f 1 f 0.1 f 03751- 039 f i gure 38. r e c o m m e nded c i rcuit conf i g ur ati o n
ad9949 rev. b | page 31 of 36 drivi n g th e cli inpu t the ad9949 s mas t er c l o c k in p u t (cli) ma y be us e d in tw o dif f er en t co nf ig ur a t io n s , d e p e ndin g on t h e a p plica t io n. f i gur e 41 sh o w s a typ i cal dc -cou p l ed in p u t f r o m t h e mas t er c l oc k so ur ce . w h en t h e d c - c o u p l ed t e c h ni q u e is used , t h e mas t er c l o c k sig n al sh o u ld be a t s t anda r d 3 v c m os log i c lev e l s. a s sh o w n in f i gur e 42, a 1000 pf ac-co u p l in g c a p a ci t o r m a y b e used betw ee n t h e c l ock so ur ce a n d t h e c l i i n p u t . i n thi s co nf igura t io n, t h e c l i i n p u t is s e lf- b ias e d t o t h e p r o p er dc v o l t - a g e le ve l o f a p p r o x ima t e l y 1.4 v . w h en t h e ac-c o u ple d t e ch- niq u e is us e d , t h e mas t er c l o c k sig n al can b e as lo w as 500 mv in am pli t ud e . ccd imager signal out h2 rg h3 h4 h1 h2 h1 rg ad9949 ccdin 03751-040 18 19 14 15 21 27 f i g u re 39. c c d co n n ec t i ons (2 h- cl ock ) 03751-041 ccd imager signal out h4 rg h1 h2 h3 h4 h2 h1 h3 rg ad9949 ccdin 14 15 18 19 21 27 f i g u re 40. c c d co n n ec t i ons (4 h- cl ock ) 03751-042 cli ad9949 25 asic master clock f i gur e 4 1 . cli c o nne c ti on, dc- c oupl ed lpf 1nf 03751- 043 cli ad9949 25 asic master clock f i gure 42. cli co nn ec tio n , a c - c oup l ed horizontal timing se quence example f i gur e 43 sh o w s a n exa m ple c c d la yo ut. th e ho r i zo n t al r e g i s t er co n t ains 28 d u mm y p i xe ls, which o c c u r o n eac h l i n e clo c k e d f r o m t h e c c d . i n t h e ver t ical dir e c t io n, t h er e a r e 1 0 opt i c a l bl a c k ( o b ) l i ne s at t h e f r on t of t h e re a d out a n d t w o at t h e b a ck o f t h e re ado u t . t h e h o r i zon t a l dir e c t ion has fo ur ob p i xe ls in t h e f r o n t an d 48 in t h e b a ck. t o co nf igur e the ad9949 h o r i zo n t al sig n als f o r this ccd , t h r e e seq u en ce s ca n b e used . f i gur e 44 s h o w s t h e f i r s t seq u en ce th a t sh o u l d b e us e d d u r i n g ver t i c a l b l a n k i ng. d u r i ng t h is t i m e , t h er e a r e n o val i d o b p i xe ls f r o m t h e s e n s o r , s o t h e c l po b sig n al is not u s e d . p b l k m a y b e e n abl e d d u r i ng t h i s t i m e , b e c a u s e no va li d da t a is a v ai la b l e. f i gur e 45 sh o w s t h e r e co m m e nde d s e q u e n ce fo r t h e ver t ic a l ob in t e r v a l . th e clam p sig n als a r e us e d acr o s s t h e w h ole lin e s in o r d e r t o s t a b ilize th e c l a m p loo p o f th e ad9949. f i gur e 46 sh o w s t h e r e co mme nde d s e q u e n ce fo r t h e ef fe c t i v e p i xe l r e ado u t. th e 48 o b p i xe ls a t t h e end o f eac h lin e a r e us e d fo r t h e clp o b sig n a l .
ad9949 rev. b | page 32 of 36 v h use sequence 2 use sequence 3 sequence 2 (optional) horizontal ccd register effective image area 2 8 dummy pixels 48 ob pixels 4 ob pixels 10 vertical ob lines 2 vertical ob lines 03751-044 f i g u re 43. e x a m pl e c c d conf ig u r at ion vertical shift vert shift sequence 1: vertical blanking ccdin shp shd h1/h3 h2/h4 hblk pblk clpob dummy invalid pixels invalid pix 03751-045 f i gure 44. h o r i zont al s e qu ence d u r i n g v e r t ic a l b l ank i ng vertical shift vert shift sequence 2: vertical optical black lines ccdin shp shd h1/h3 h2/h4 hblk pblk clpob optical black dummy optical black 03751-046 f i g u re 45. h o r i zont al s e qu ences d u r i n g v e r t ic a l o p t i c a l b l a c k p i x e ls
ad9949 rev. b | page 33 of 36 vertical shift vert shift sequence 3: effective pixel lines ccdin shp shd h1/h3 h2/h4 hblk pblk c lpob optical black dummy effective pixels ob optical black 03751-047 f i gure 46. h o r i zont al s e qu ences d u r i n g e ffec t ive p i x e ls
ad9949 rev. b | page 34 of 36 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bcs sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 re f 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (b o t t o m view) compliant to jedec standards mo-220-vjjd-2 f i gure 47. 4 0 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] 6 mm 6 m m b o d y (c p - 4 0 ) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ad9949kcp ?20c to +85c 40-lead lead fr ame chip scale package (lfcsp) cp-40 ad9949kcprl ?20c to +85c 40-lead lead fr ame chip scale package (lfcsp) cp-40 AD9949KCPZ 1 ?20c to +85c 40-lead lead fr am e chip scale package (lfcsp) cp-40 AD9949KCPZrl 1 ?20c to +85c 40-lead lead fr am e chip scale package (lfcsp) cp-40 ad9949akcpz 1, 2 ?20c to +85c 40-lead lead fr am e chip scale package (lfcsp) cp-40 ad9949akcpzrl 1, 2 ?20c to +85c 40-lead lead fr am e chip scale package (lfcsp) cp-40 1 z = pb-fre e part. 2 the ad9949a is recommended fo r new designs and sup p orts ccd line leng ths > 4096 pixels.
ad9949 rev. b | page 35 of 36 notes
ad9949 rev. b | page 36 of 36 notes ? 2004 a n alog devic e s , inc . a ll rig h ts r e s e r v e d . t r a d ema r ks and re g i s - t e r e d tr ad emarks ar e th e proper t y of their r e spec tiv e o w ners. d03751C0C 11/04(b)

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